Stacked multi-level or “3D” integrated circuits offer several advantages over conventional 2D integrated circuits, such as lower power consumption, faster performance, reduced physical area consumption and package size. Typically, a 3D integrated circuit includes through-silicon vias (TSVs) that facilitate transferring data from one die to another die stacked against the first. Thus, testing of TSVs for electrical integrity should be done before and after stacking the dies to ensure the proper functionality and high manufacturing quality of the 3D integrated circuit.
Desirable in the art is an improved circuit and method for testing through-silicon vias (TSVs) that would improve upon the conventional circuit and method as to these and other aspects.